[LMH] E1 MCR interrupt bits?

[nyef@lisphacker.com]

Brad Parker writes: 

> Can someone explain know the interrupt scheme on the E1 works? 
> 
> I assume the e00000-e0003e register space on the cpu is for interrupt
> testing only, i.e.  nubus cards don't write to this space, only the
> diags do.

Bad assumption, I'm afraid. SSDN2, section 3.2 says that NuBus cards do 
exactly this. 

> Do the NUPI and SIB assert a nubus hardware interrupt?  Does the cpu
> hardware see than and place it in it's list of pending interrupts?

No, the NuPI and SIB are bus-master-capable, and are instructed by the CPU 
as to which word address they are to write the value 1 to when they wish to 
signal for attention. 

> I see that the cpu manages pending interrupts on a priority basis from
> 15-0 with 0 being the highest.  I don't quite get how the microcode
> resets the pending interrupts or how the are asserted in the normal
> case.

Pending interrupts are reset by writing a 0 to the appropriate spot in the 
CPU register space. 

> -brad

 --Alastair Bridgewater