[LMH] E1 MCR interrupt bits?

[Brad Parker]

Can someone explain know the interrupt scheme on the E1 works?

I assume the e00000-e0003e register space on the cpu is for interrupt
testing only, i.e.  nubus cards don't write to this space, only the
diags do.

Do the NUPI and SIB assert a nubus hardware interrupt?  Does the cpu
hardware see than and place it in it's list of pending interrupts?

I see that the cpu manages pending interrupts on a priority basis from
15-0 with 0 being the highest.  I don't quite get how the microcode
resets the pending interrupts or how the are asserted in the normal
case.

-brad