[LMH] Ooh, look! List traffic!

[Nyef]

On Fri, Mar 05, 2004 at 09:46:02AM -0500, Mark J. Dulcey wrote:
> Jaap Weel wrote:
> 
> >Question: What is the Exploder microcode instruction set like? Is it 
> >*much* different, conceptually, from CADR microcode? This would 
> >determine the amount of FPGA area needed to implement the controller. If 
> >it's anything like the CADR, my hunch is: not much.
> 
> I don't have any direct knowledge of the TI Explorer architecture, but I 
> believe it's similar.

It is similar. In some ways more complex, in some ways simpler.

> Like all machines in the LMI branch of LispM heritage, the Explorer and 
> uExplorer had 32 bit words.

All Explorers had 32-bit data words. The Explorer I used a 56-bit
microinstruction word, and the later systems used a 64-bit
microinstruction word.

> >Question: How much microcode is there? I.e. how much microcode RAM do 
> >you need?

For the Explorer I, it is #x800 words for the startup microcode and
#x4000 words for the writable microcode store. The Explorer I also needs
#x40 words of M-memory, #x400 words of A-memory, 16 words of T-memory,
#x1000 words of D-memory, 64 words of microstack, #x1000 words of level-1
map memory, #x1000 words of level-2 map control memory, #x1000 words of
level-2 map address memory, and #x400 words of PDL-buffer memory. The
microcode stores use a 56-bit word, the microstack uses something a bit
less than 32 bits (I forget what, was it 17 bits?), and everything else
uses 32-bit words.

--Alastair Bridgewater