[LMH] Ooh, look! List traffic!

[Jaap Weel]

On 4 Mar 2004, at 18:57, Dan Moniz wrote:
> On Thursday, March 04, 2004 7:01 PM +0000 Robert Swindells 
> <rjs@fdy2.demon.co.uk> wrote:
>> I was only half joking about translating it to VHDL.
>> [...]
>> The whole CPU would fit into a $15 FPGA using current technology, add
>> a couple of 16bit SDRAMs and some boot flash and you have a 10x faster
>> microExplorer.
>
> [...]
> Of course, there's the longer term problem of getting a monitor and 
> input devices to talk to it, which would be painful, and disks, file 
> systems, a running install, oh my!
> Probably, now that I think about it, an FPGA-based Explorer processor 
> on a PCI card, with some interface glue would be the way to go.

I don't know if this is applicable, but hey, you never know. When they 
made OpenGenera (you know, the virtual Symbolics-on-Alpha), they didn't 
give it any intrinsic knowledge about DEC's hardware. All it knew how 
to do was to talk on the network. It would then find its filesystem 
through NSF, display its interface through X11, and in various other 
ways leverage the fact that there was always a copy of OSF/1 to take 
care of bit-diddling IO. It's not very purist, but you could do a lot 
with a network interface, while a $200 Walmart FORTRAN Machine can take 
care of I/O.

> If someone is willing to buy me a simple Xilinx setup (usable FPGA for 
> this purpose, test-board, Verilog compiler, etc.), I'll take a crack 
> at it. I won't hold my breath, but this equipment has come down in 
> price. I think the FPGA we'd want/need is more expensive than the one 
> included in their $70 - $100 starter kit.

In all the following, please keep in mind that I just happen to have 
become interested in FPGA's like, what, three weeks ago, so don't take 
any of this to literally:

Xilinx development boards are overpriced and geared towards industries, 
not hackers or students; third-party suppliers are cheaper. Some of 
their boards come as PCI cards, which would be a Good Thing. There's 
www.geda.seul.org for various GPL'ed design tools, including a Verilog 
simulator. Xilinx put out a student edition of their software that you 
can order on Amazon for $65. It contains VHDL and Verilog tools as well 
as lower-level tools. It has a limitation on the size of FPGA it can 
deal with, but I don't think that need be prohibitive. It says for an 
older version: "any XC9500 CPLD, any Spartan FPGA, any XC4000 FPGA up 
to an XC4010, or the XCV50 Virtex FPGA." Spartan goes up to 28*42 CLB's 
with 56kbits on-chip "block ram". The d*(&%^*& Xilinx website is down 
so I can't check what the limitations on the current version are or how 
many CLB's are on a Virtex.

At the risk of seriously offending the intellect of readers who know 
computer architecture much better than I do from just reading 
Hennesy&Patterson:
  Even though on LISP machines the microcode has the added advantage 
that it can be reprogrammed easily, the original reason for Microcode 
as opposed to Hardwired Control is that you could conserve precious 
silicon area by having a really simple control unit (in the CADR, 
practically none, since the microcode instruction set is notoriously 
simple; I don't know much about the Exploder, but I imagine it's 
similar). This is why I'm not too worried about needing humongous 
amounts of silicon. Many FPGA's have built-in fast RAM that could 
contain microcode.

Question: What is the Exploder microcode instruction set like? Is it 
*much* different, conceptually, from CADR microcode? This would 
determine the amount of FPGA area needed to implement the controller. 
If it's anything like the CADR, my hunch is: not much.
Question: What is the word length on a uExploder again? (I'm sorry, I 
can't ever keep the word lengths of all different LISP machines 
detangled in my head.) The size of the datapath part of a design should 
scale about linearly in the word length. Of course, it also depends on 
how many different operations you need to do, how many registers you 
need &c.
Question: How much microcode is there? I.e. how much microcode RAM do 
you need?

It is my impression, but then again, I am by no means well-versed in 
this stuff (yet), that "naive" Verilog coding and then letting a 
synthesis program figure out which wires go where decreases performance 
by a factor of something manageable but annoying, and that people 
prefer to tweak their code, potentially later on in the process, to get 
better cycle times. For example, the LEON-1 SPARC implementation from 
ESA (http://www.estec.esa.nl/wsmwww/leon/) is written in portable VHDL, 
independent of the flavor of silicon. It runs at 45 MHz on a biggish 
Xilinx, but only "after layout", which I *assume* means after somebody 
who knew his Xilinx stuff gave extra hints to the Xilinx software as to 
what to put where and maybe tweaked some of the code. To do that, you 
would probably need simulation tools that come with your FPGA, which 
implies buying them from Xilinx. To just get working Verilog code, you 
could probably use the free Ikaros simulator.

I'm trying to get into the whole FPGA thing because I'm supposed to 
implement a CPU in one for my summer job. There have been various 
reports from people doing interesting projects in surprisingly little 
time given the right tools; look up fpgacpu.org for some pointers and 
lots of FPGA shop talk. Especially his circuit cellar article gives a 
good idea of the practicalities involved, I think. Once again, he's 
doing RISC-like hardwired control, not microcoded control. I don't know 
if anyone has tried microcoded control yet.

	/jaap

========================================================================
Jaap Weel                   Campus address:        | dorm (626) 795-9748
Caltech, Blacker '05        Caltech MSC #874, Pasadena, CA 91126, U.S.A.
www.its.caltech.edu/~weel   Permanent address:     | home +31-46-4337033
E-mail: weel@caltech.edu    Kelderstraat 2-4, 6171 GB Stein, Netherlands
========================================================================