[LMH]More microcode fun...

[Paul Fuqua]

    Date: Sat, 27 Apr 2002 10:03:58 -0500 (CDT)
    From: Daniel Seagraves <dseagrav@sakura.lunar-tokyo.net>
    
    First, in the case of 20-37:
    Is the named location (VMA or MD) where the data goes/comes from, or is it
    where the address is/comes from?

Typically one would read from memory by writing the address to
VMA-Start-Read;  some cycles (four for Explorer I, I don't know about
Explorer II) later the data would appear in MD.  Unless there was a page
fault;  E2 would abort and the page-fault-handler would take it over, E1
would check status explicitly and do the same thing.

I can't remember offhand if for writes we'd set up the address (in VMA)
first or the data (in MD);  either way, the -start-write destination
would trigger the operation.

The "normal" forms used virtual addresses and went through the page maps
(I think);  IO space was a separate area in the address space, though I
forget what we used it for;  "unmapped" forms skipped the page maps;
"NUBUS" forms must have been direct NuBus reads.

NuBus boards used memory-mapped control;  reading and writing to
specific addresses on a board made it do specific things.  I'm not sure
where all that is documented.  NuBus addresses on the Explorer were
#xFsaaaaaa where "s" is the slot number and "aaaaaa" is the address.  I
remember being able to make a displaced-to-physical array to the right
place and having a back door to the screen memory.
    
    Which bus does this deal with?  Is this the Explorer private bus, or is
    it some kind of memory-mapped IO-Space like the PDP-11 has?

Effectively, everything is NuBus;  E1 had a local bus to memory, but
that was just for speed and I'm not sure if E2 even used it.
    
    Next, 60-77:
    Same question, is the named register the data or address?
    What do they mean by "transport"?

Same mechanism.  "Transport" is a GC term;  my rusty memory says it was
something one did after reading the datum, to make sure any forwarding
pointers were followed correctly.  The chip spec says the numbers were
transport codes shown on external pins, but I frankly can't remember
using them;  I wonder if they appear in the microcode.
    
    I gather the two-operand micro-operations (Add, etc.) get a source
    from both the A-bus and M-bus - But which bus is used for single-operand
    microinstructions?

Can't remember without looking it up, but logic suggests one of (a)
A-bus or (b) obvious from context -- only A can reach the higher parts
of A-memory, but only M can reach the functional destinations.  I'll
look it up when I get home.

                              pf