[LispM-Hackers] FYI about read barriers and x86 architecture

[ford@objs.com]

Cool!

John Morrison wrote:

> Hi;
>
> Just FYI: it seems that it might be possible to have a hardware-based
> read barrier for a "supervisor" (protection level 0) program.  Rumour
> has it that, if you enable 4MB pages (and maybe enable 36-bit physical
> addresses -- or not -- the various information sources conflict), then
> you can force the CPU to generate a page fault if some of the "reserved
> and should be zero" bits in either the page directory or page table
> entries are set to one.  The bad news is that this behavior apparently
> only is exhibited by Pentium or later CPUs, and maybe by some late-model
> 486s.
>
> I do not plan to test this right now, but it's interesting to know that
> it exists.  (The other plan would be to set up some weird segmentation
> thing, or set up another task, or some other such Intel weird way of
> doing things, all of which strike me as fabulously over-complicated.)
>
> -jm
>
> --
> ==== John Morrison
> ==== MAK Technologies Inc.
> ==== 185 Alewife Brook Parkway, Cambridge, MA 02138
> ==== http://www.mak.com/
> ==== vox:617-876-8085 x115
> ==== fax:617-876-9208
> ==== jm@mak.com
>
> http://lists.unlambda.com/mailman/listinfo/lispm-hackers

--
Steve Ford
Object Services and Consulting, Inc.
225 State Rd
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