Software Design Notes Data Structures APPENDIX A Data Structures A.1 NONVOLATILE RAM (NVRAM) A.1.1 NVRAM Data Structure Definitions. The NVRAM data structures may be divided into several independant sections. The first section contains information about the location of resources (monitor, keyboard, and load device) required for system testing and booting. The next section contains information about the last system shut down, including cause of shutdown, when the previous system boot occured, and how long the system was running before it shutdown. Crash record "registers" make up the next section, providing control for a circular buffer of crash records (the crash record buffer is located in the same NVRAM, after additional standard sections). Following the crash record registers are sections which provide for dynamic allocation management of the rest of the NVRAM, including the "typed block" area. A.1.1.1 Test and Boot Resources. The NVRAM contains values which the System Test and Boot Master (STBM) references in order to find preselected resources. The NuBus slot and a 24 bit logical unit number are provided for a monitor, a keyboard (to be used for user interaction), and a default load source (to be used if a default system load occurs). Since the NVRAM contents may be invalid if the NVRAM has not been initialized or if the battery runs low, it is necessary to validate the contents of the NVRAM before they are used. Three mechanisms are provided for this function, although all may not be used in some implementations. First, the NVRAM data structure format generation and revision are stored so that they may be validated. The format generation should never change from >01 if it conforms to this specification, but the revision may change as features are added to the NVRAM such that they are upward compatable. Second, the test and boot resource information and the format generation and revision fields are (optionally) protected by a 16 bit CRC value. The CRC calculation method used is identical to that used in the Configuration ROM and provides protection for the first 14 bytes of the NVRAM. Finally, a configuration checksum (optionally) is stored in the NVRAM so A-1 Data Structures Software Design Notes that the chassis configuration can be verified as being unchanged from when the NVRAM test and boot resources information was last updated. A.1.1.2 Last Shutdown Information. Information is (optionally) stored in the NVRAM that can be used following a system boot to determine information about the previous system boot and shutdown. The shutdown information includes date and time of last boot, how long the system was running before the shutdown, and cause of the shutdown. After the operating system reads and logs the information in the shutdown fields from the previous system boot, it should update them to reflect the current boot date and time. Then the time since boot should be updated preiodically (at least once per minute) so that it is current if an unexpected shutdown occurs. When a system shutdown occurs the shutdown cause should be logged in the NVRAM and the shutdown information valid character set to allow the next boot operation to determine that the shutdown cause was correctly recorded. A.1.1.3 Crash Record Registers. The Crash Record Registers are a set of dedicated NVRAM locations that provide a control structure for a circular buffer (located in the NVRAM) where a system processor stores a predefined set of information when it detects a system crash condition. Since it is desirable for there to be a history of several previous crashes stored in the NVRAM at one time, the buffer must be managed such that at anyt ime a new crash record can be added to the buffer, and so that system software can retrieve the crash history without confusion. The Crash Record Registers provide the data necessary for this management function. They include information about the crash record format and size, buffer location in NVRAM and size (pointers to the beginning of first and last records), and a pointer to the currently active crash record. A.1.1.4 Typed Blocks. It is desirable to be able to access, allocate and deallocate areas of the NVRAM as needed without disturbing other allocated data structures. NVRAM Typed Blocks provide a generic mechanism for accessing, allocating, and deallocating variable length blocks of NVRAM. Typed Blocks are used to manage the entire NVRAM, excluding the fixed system parameters in the first 64 bytes (offsets 00-FF). The size of Typed Blocks are determined as they are allocated, so that they can be customized to the needs of particular applications. In order to support the required operations, each Typed Block contains: reserve block Block Type Number 16-bit, uniquely identifies the use of each Typed Block A-2 Software Design Notes Data Structures Block Length 16-bit, specifies the entire byte length of each Typed Block, inclusive of the Block Type Number, the Block Length, and Block Data Block Data Application specific data format and content The Block Type Number and Block Length are used during searches through NVRAM for any specific kind of Typed Block. The Block Type Number provides for the unique recognition of blocks while the Block Length is used to determine the location of the start of the next block. Block Type Numbers are unique, assigned numbers that designate the use of each Typed Block. Two Block Type Numbers are reserved for the generic functions of Available and End, a range is reserved for TI use, and the remainder are available for assignment to NuBus license holders upon request. Assigned block type numbers are recorded in TI drawing part number 2549287-0001. Block Type Number >FFFF indicates that a Typed Block is currently Available to be allocated. Zero or more Available blocks may be present at one time in each NVRAM. If no Available blocks are present then there is no remaining space for expansion (unless some already allocated block is removed and its space recovered). Multiple Available blocks may result from deallocation of previously used blocks. Block Type Number >FFFE indicates the End Block, which marks the end of the NVRAM area dedicated for Typed Blocks. No allocation of NVRAM space shall extend beyond the End Block. Normally the End Block has a Block Length of four (i.e., zero length data section) and is placed in the last four bytes of an NVRAM. A Typed Block of any particular Number is found by searching through the NVRAM starting at offset >100. Each block's Type Number found is compared with the desired number and the End number (>FFFE). If the End block is found before the desired block, then none has been allocated. If the current block is neither the desired block or the End block, add the Block Length of the current block to the current offset and check the next block. Typed Block allocation and deallocation is done by changing the Type Block Number of an already existing block and adjusting the Block Lengths. Allocation is done by "carving" an application block out of an Available block. Deallocation is done by returning any block to the Available mode. Note that the allocation operation must be done in coordination with all other A-3 Data Structures Software Design Notes processors in the system such that a collision does not occur by two processors attempting to allocate the same, previously Available block. This is easily accomplished by each processor during the boot process while each processor is loading itself as either the Primitive or as a Secondary but before reacking the Synchronization Point. A.1.1.5 NVRAM Format. The following provides specific information about the NVRAM standard data structures: System default configuration information: ----------------------------------------- base +>00= STBM Monitor Unit number LSB byte Binary base +>04= STBM Monitor Unit number MID byte Binary base +>08= STBM Monitor Unit number MSB byte Binary base +>0C= STBM Monitor slot number (FF= none) Binary base +>10= STBM Keyboard Unit number LSB byte Binary base +>14= STBM Keyboard Unit number MID byte Binary base +>18= STBM Keyboard Unit number MSB byte Binary base +>1C= STBM Keyboard slot number (FF= none) Binary base +>20= Boot source device unit LSB byte Binary base +>24= Boot source device unit MID byte Binary base +>28= Boot source device unit MSB byte Binary base +>2C= Boot source device slot (FF= none) Binary base +>30= NVRAM format generation number. Equal >01 for all NuGeneration devices. Binary base +>34= NVRAM format superset revision number. Binary base +>38= NVRAM CRC LSB byte Binary base +>3C= NVRAM CRC MSB byte Binary CRC calculated same as for Config. ROM except it does not cover the entire NVRAM, rather only the system configuration information in the range base +>00 through base + >34. Configuration Checksum ---------------------- base +>40= Config. Checksum LSB byte Binary base +>44= Config. Checksum MSB byte Binary 16 bit sum (overflow ignored) generated by adding together all 16 bytes of the Part Number field of every slot Configuration ROM. If a slot is empty or does not appear to contain a Configuration ROM then it does not affect the checksum. This value may be used to verify that the A-4 Software Design Notes Data Structures system configuration has not changed. (note that moving a board to another slot does not change the checksum). base +>48= reserved for use as Synchronization Flag by STBM base +>4C= reserved for use in board tests of NVRAM A-5 Data Structures Software Design Notes last shutdown information: -------------------------- base +>50= Abnormal Shutdown Valid character. Set to ASCII "V" (>56) if valid shutdown information was stored ASCII base +>54= shutdown cause: Binary >00= overvoltage shutdown >01= undervoltage shutdown >02= overvoltage after high temperature >03= high temperature shutdown >04-FF= reserved base +>58-5C reserved base +>60= month of BOOT. (Jan=1, Feb=2...) Binary base +>64= day of month of BOOT (1..31) Binary base +>68= hour of day of BOOT (0-23) Binary base +>6C= minute of hour of BOOT (0-59) Binary base +>70= Seconds since BOOT LSB byte Binary base +>74= Seconds since BOOT Binary base +>78= Seconds since BOOT Binary base +>7C= Seconds since BOOT MSB byte Binary crash records registers: ------------------------ base +>80= Crash Record Format Processor type LSB Binary base +>84= Crash Record Format Processor type MSB Binary base +>88= Crash Record Format Revision Binary base +>8C= reserved base +>90= Currently Active crash record LSB Binary base +>94= Currently Active crash record MSB Binary base +>98= Crash Record Size LSB byte Binary base +>9C= Crash Record Size MSB byte Binary base +>A0= Crash Record Buffer, last record LSB Binary base +>A4= Crash Record Buffer, last record MSB Binary base +>A8= Crash Record Buffer, first record LSB Binary base +>AC= Crash Record Buffer, first record MSB Binary base +>B0-EC= reserved A-6 Software Design Notes Data Structures NVRAM Typed Blocks List: ------------------------ base +>100 Start of NVRAM Typed Blocks typed block format (starting at NVRAM base + >100 ): ----------------- block + >0= Block Type Identifier LSB byte Binary block + >4= Block Type Identifier MSB byte Binary controlled to be unique 16 bit number identifiing block type: 0000-0007= reserved for TI diagnostics 0008-000F= reserved for TI Lisp 0010-0017= reserved for TI S1500 (tm) (S1500 is a trademark of Texas Instruments Incorporated.) 0018-00FF= reserved for TI 0100-FFFD= available for assignment, see TI drawing 2549287-0001 FFFE = End block FFFF = Available block block + >8 Block Length LSB byte Binary block + >C Block Length MSB byte Binary block + >10... Block Data (application specific) A-7 Data Structures Software Design Notes A.2 DISK PARTITION STRUCTURES There are several standard partitions (contiguous sections of the allocatable media) defined on disk. These include the Volume Label, Partition Table, Save Partition, Test Zone, and Format Information partition. The following sections briefly describe the function of each. NOTE All partition addresses below are expressed in blocks. A block is 1024 bytes. A.2.1 Volume Label Partition. Each volume contains a variety of partitions which are accessed through a minimal "directory" whose root is the volume label. The label, in logical block 0 of the volume, is the only partition with a fixed location. All other partition locations are determined indirectly via pointers found in first the label, then in the Partition Table. The label contains information about the physical and logical characteristics of the volume and also provides pointers to the Save and Partition Table partitions. The second block of the label (logical block 1) is reserved as a fixed location, emergency data "save" area of exactly one block length. Use of this block is system implementation dependent. It is not an actual partition (as is the Save partition) but rather just a spare block with a known address. A.2.2 Partition Table Partition. The Partition Table provides name, characteristics, pointer and size information for each partition on the volume. The first section of the Partition Table provides information about the table format, such as number of partitions in the table, size of each entry, and offset in each entry to comments. Following the format information table is the table of individual entries describing each partition. Each entry in the table has a set of partition "key" characteristics. These include: * Name of the partition A-8 Software Design Notes Data Structures * Partition Type * Partition User Type * Partition attribute bits Any combination of the characteristics may be used to uniquely identify a particular partition. For example, a partition with a particular Name (MCR1), Partition Type (>01=microload), and User Type (>0000=Explorer) may be found, even though other partitions may have the same Name or Partition or User Type. Likewise, the default partition, identified by the default bit (Default attribute=1), Partition Type (>01=microload), and User Type (>0000=Explorer) can be located regardless of what Name the partition may have (this is the mechanism used in the booting process to locate default partitions of specific types). Several comments about partitions and key values are in order: 1. Name + Partition Type + User Type combinations should be unique, however, a single Name may well be used again for a different Partition Type and/or User Type, and obviously both Partition and User Type shall be used many times. 2. Multiple entries in the table may point to the same physical partition with different key characteristics being used to identify the partition. 3. All searches through the partition table are assumes to start at the beginning of the table and continue until either a match of the desired key characteristics occurs or the end of the table is reached. 4. The order of the entries in the partition table does not imply information about the physical order of partitions on the volume. 5. Zero length partitions are allowed, and indeed are sometimes used as "markers". 6. There may be space on the volume that is not allocated to any partition, and therefore does not appear in the table. A.2.3 Test Zone Partition. The Test Zone Partition (TZON) is provided to accommodate testing the hardware. It is used to access the volume without disturbing system or user data. It includes fixed data patterns that can be used to test data read channels and blocks that are reserved for A-9 Data Structures Software Design Notes write-then-read tests to check write channels. This partition is vital for providing device maintenance; it should never be removed from any volume. A.2.4 Format Information Partition. The Format Information Partition (FMT) contains details about the way the volume media was tested and formatted. Several sections of data are recorded, including physical sector and track data formats, surface analysis methods used, and detail lists of defects found when the media was initialized. This partition also should never be removed or destroyed. Also, it should not be copied from one disk to another - it is device specific. A.2.5 Partition Descriptions. For the following partition layouts, these notes apply. 1. All "text" is in the form of ASCII strings, with the characters read left to right stored in ascending byte address order. 2. It is important that any "text" contain only standard characters (i.e., no special escape or control ASCII characters) in order to provide for portability of the disk between the expected variety of Nu Generation (tm) systems. (Nu Generation is a trademark of Texas Instruments Incorporated.) 3. All four character "text" fields must contain valid ASCII characters in all positions. 4. Comment fields contain "text" of variable length within the maximum field length, with a byte of >00 after the last character of "text". Any remaining characters following the >00 to the end of the field are garbage. 5. In the following description the following abbreviations are used: a. LSB = least significant byte b. DML = middle low byte c. MDH = middle high byte d. MSB = most significant byte e. "X" = an ASCII character f. xxxx xxxN = indicates bit position within a byte A-10 Software Design Notes Data Structures g. >0 = all bits set to zero 6. All numbers are unsigned binary values (unless otherwise defined). A-11 Data Structures Software Design Notes ============================================== Volume Label ============================================== Label description (block #0): offset value ---------------------------- ------------- 1. "LABL" (4 ASCII character) +000 "L" +001 "A" +002 "B" +003 "L" 2. Revision in four bytes: (number) +004 LSB byte +005 MDL byte +006 MDH byte +007 MSB byte 3. Reserved (0's, as for all reserved +008-00F >0 unless stated otherwise) Type storage: ------------- 4. Flag word: bit: 210 4a. Bit 0-2 typecode: 000=disk +010 xxxx xNNN 001=tape 7654 3210 010=Wrt-Once-Rd-Many (WORM) 011-111=reserved 4b. Bit 3 fixed: 0=removable; 1=fixed +010 xxxx Nxxx 7654 3210 4c. Bit 4 logical: 0=phys addr; +010 xxxN xxxx 1=logical addr 7654 3210 ----------tape------------------------------ bit: 765 4d. Bit 5-7 tape opt: 000=stream only +010 NNNx xxxx 001=start/stop 7654 3210 010=stream w/track select 011=start/stop w/track select 100-111=reserved ----------disk------------------------------ 4e. Bit 5-7 reserved +010 NNNx xxxx 7654 3210 ----------disk and tape--------------------- 4f. bit 8-31 reserved +011-013 >0 5. Device name text (e.g., MAX-0140; +014 "M" CDC-0030) OR reserved ( if reserved +015 "A" = >0 ) : : +01F " " A-12 Software Design Notes Data Structures Addressing: ----------- 6. # of bytes/block (required for partition +020 LSB byte table) +021 MSB byte ----------disk------------------------------ 7. # of bytes/sector +022 LSB byte +023 MSB byte 8. Reserved +024-025 >0 9. # of sectors/track +026 byte 10. # of heads (tracks/cyl) +027 byte 11. # of cylinders +028 LSB byte +029 MSB byte 12. # of reserved sectors for defects* +02A LSB byte +02B MSB byte * = note that the above parameters are used to calculate device maximum capacity by the following equation: total 1k blocks = (((#cyls * tracks/cyl * sectors/track) - (#reserved sectors)) * bytes/sector) / 1024 13. Reserved +02C-02F >0 ----------tape------------------------------ 14. # of bytes/physical block +022 LSB byte +023 MSB byte 15. Reserved +024-025 >0 16. # of tracks (if supported) +026 LSB byte +027 MSB byte 17. # of blocks (nominal) +028 LSB byte +029 MDL byte +02A MDH byte +02B MSB byte 18. Reserved +02C-02F >0 19. Volume name (16 characters of text ) +030 "N" +031 "A" +032 "M" +033 "E" A-13 Data Structures Software Design Notes +03F "X" 20. Reserved +040-04F >0 21. Partition table name = "PTBL" +050 "P" +051 "T" +052 "B" +053 "L" 22. Starting block address of partition table +054 LSB byte +055 MDL byte +056 MDH byte +057 MSB byte 23. Length of partition table in blocks +058 LSB byte +059 MDL byte +05A MDH byte +05B MSB byte 24. Reserved for additional partition table +05C-06F >0 information 25. Secondary SAVE store partition name = +070 "S" "SAVE" +071 "A" +072 "V" +073 "E" 26. Starting block address of secondary SAVE +074 LSB byte partition +075 MDL byte +076 MDH byte +077 MSB byte 27. Length of secondary SAVE partition in +078 LSB byte blocks +079 MDL byte +07A MDH byte +07B MSB byte 28. Reserved for additional secondary SAVE +07C-08F >0 store information 29. Reserved for future label information +090-0FF >0 30. Volume comments, text +100-3FF "X" A-14 Software Design Notes Data Structures Label Save Store (Block #1) ----------------------------- NOTE: There is only a single block #1 save store. Therefore, its use must be very carefully controlled in multiprocessor system to prevent problems. 31. Internal SAVE contents are processor specific. A-15 Data Structures Software Design Notes =============================================== PARTITION TABLE (PTBL) offset value ===============================================------------- 1. "PRTN" (identifier reserved for partition +000 "P" table) Note: This is not the partition table name, +001 "R" but rather a value used to identify a +002 "T" valid partition table. +003 "N" 2. Partition table revision number +004 LSB byte +005 MDL byte +006 MDH byte +007 MSB byte 3. Number of partitions in partition table. +008 LSB byte +009 MDL byte +00A MDH byte +00B MSB byte 4. Size of each partition table entry in long +00C LSB byte words (32 bit words) +00D MDL byte (for current revision = >00000010) +00E MDH byte +00F MSB byte 5. Offset in long words (32 bit) to comment +010 LSB byte (for current revision = >00000004) +011 MDL byte +012 MDH byte +013 MSB byte 6. Reserved for additional partition table +014-03F >0 information A-16 Software Design Notes Data Structures Partition table entries: (length may vary with revision) ========================================================= 7. Partition name (ASCII string) entry +000 "N" entry +001 "A" entry +002 "M" entry +003 "E" 8. Partition start address in blocks entry +004 LSB byte entry +005 MDL byte entry +006 MDH byte entry +007 MSB byte 9. Partition length in blocks entry +008 LSB byte entry +009 MDL byte entry +00A MDH byte entry +00B MSB byte Partition attributes: ===================== 10. Byte 0: generic function type code: entry +00C byte * 00= load band (processor specific) * 01= microload band (processor specific) 02= page band (processor specific) 03= file band (operating system specific) 04= meter band (processor specific) 05= test zone band (generic) 06= format parameter band (generic) * 07= volume label (generic) 08= save band (generic) * 09= partition band (generic) * 0A= configuration band (generic) 0B= user defined type #1 (processor/O.S. dependent) 0C= user defined type #2 (processor/O.S. dependent) 0D= user defined type #3 (processor/O.S. dependent) 0E= user defined type #4 (processor/O.S. dependent) 0F= user defined type #5 (processor/O.S. dependent) 10= user defined type #6 (processor/O.S. dependent) 11= user defined type #7 (processor/O.S. dependent) 12= user defined type #8 (processor/O.S. dependent) 13= user defined type #9 (processor/O.S. dependent) 14= user defined type #10 (processor/O.S. dependent) 15-FE= reserved FF= empty (generic) * = One partition of this (function type)/(CPU type) is expected to have the "Default" bit set. A-17 Data Structures Software Design Notes 11. Byte 1,2: USER type: entry +00D LSB byte Unique CPU numbers assigned to each entry +00E MSB byte processor or unique operating sys./class values: >0000-EFFF: range for CPU identifiers. Same as "type of processor" in "board type" field of configuration ROM. >F000-FBFF = reserved for additional special blocks >FC00-FEFF: range for use as operating system identifiers (unique numbers to be controlled; single numbers to be assigned upon request as needed). See TI drawing part number 2549237-0001 for a complete list. >FC00 = TI Lisp >FC01 = TI QDOS Files for S1500 >FC02 = TI S1500 >FF00-FFFF: reserved for use as magic values (unique numbers to be controlled; single numbers to be assigned upon request as needed). See TI drawing part number 2549287-0001. >FFFF = processor and O.S. independent (i.e., all "generic" bands) 12. Bytes 3 property bits (position encoded): entry +00F byte bit:31 24 12a. Bit 31=expandable (1=expandable) Nxxx xxxx 12b. Bit 30=contractable (1=contractable) xNxx xxxx 12c. Bit 29=delete protected (1=protected) xxNx xxxx 12d. Bit 28=logical partition (1=part of logical part) xxxN xxxx 12e. Bit 27=copy protected (1=protected) xxxx Nxxx 12f. Bit 26=default indicator (1=default) xxxx xNxx 12g. Bit 25=diagnostic use (1=diagnostic use) xxxx xxNx 12h. Bit 24=reserved xxxx xxxN NOTE: THESE BITS MAY ONLY BE CHANGED BY THE OWNER OF THE PARTITION ---- revisions may change what's below this line ----- 13. Partition comment text entry +010-03F "X" (always in multiples of 32-bit words) A-18 Software Design Notes Data Structures =============================================== "TZON" (Test Zone) band =============================================== 1. TZON block #0: offset value -------------- ------------ Read only test pattern of fixed values: +000 >00 (a sequence of values, incremented by 1, +001 >01 beginning at "00". The sequence +002 >02 increments to 255 (FF), and then : : restarts at 00.) +0FE >FE +0FF >FF +100 >00 +101 >01 : : +3FF >FF 2. TZON block #1: -------------- Read only test pattern of fixed values: The following pattern repeated 4 times (to fill the block): +00 +01 . . . . . . . . +0E +0F ---------------------------- +000 : >AA >AA . . . . . . . . >AA >AA +010 : >FF >FF . . . . . . . . >FF >FF +020 : >00 >04 . . . . . . . . >00 >04 +030 : >BF >FF . . . . . . . . >BF >FF +040 : >2A >E3 . . . . . . . . >2A >E3 +050 : >6A >DB . . . . . . . . >6A >DB +060 : >B6 >6D . . . . . . . . >B6 >6D +070 : >96 >A5 . . . . . . . . >96 >A5 +080 : >24 >49 . . . . . . . . >24 >49 +090 : >33 >33 . . . . . . . . >33 >33 +0A0 : >98 >31 . . . . . . . . >98 >31 +0B0 : >1A >49 . . . . . . . . >1A >49 +0C0 : >CF >23 . . . . . . . . >CF >23 +0D0 : >8F >46 . . . . . . . . >8F >46 +0E0 : >63 >53 . . . . . . . . >63 >53 +0F0 : >0A >CC . . . . . . . . >0A >CC 3. TZON blocks #2 & 3 Reserved for future read-only ------------------ patterns. 4. TZON blocks #4 - N Write/read test blocks. ------------------ Number of blocks reserved for write/read computed as ((blocks_per_track * heads_oer_cylinder) + 2) A-19 Data Structures Software Design Notes ================================================== "FMT " (Format Information) band (9K, fixed length) ================================================== FMT block #0: (read-only) offset value -------------- -------------- 1. Sector skew from head to head: +000 LSB byte +001 MSB byte 2. Sector interlace value: +002 LSB byte +003 MSB byte 3. Sector blocking within interlace factor. +004 LSB byte +005 MSB byte Sector format information: -------------------------- 4. Gap 1 size in bits: +006 LSB byte +007 MSB byte 5. Gap 2 size in bits: +008 LSB byte +009 MSB byte 6. Gap 3 size in bits: +00A LSB byte +00B MSB byte 7. Header size in bytes: +00C LSB byte +00D MSB byte 8. Data field size in bytes: +00E LSB byte +00F MSB byte 9. Header sync character (LSB justified): +010 LSB byte +011 MSB byte 10. Data sync character (LSB justified): +012 LSB byte +013 MSB byte 11. Header ECC or CRC polynomial +014 LSB byte (64 bit, LSB justified): : +01B MSB byte 12. Data ECC or CRC polynomial +01C LSB byte (64 bit, LSB justified): : +023 MSB byte 13. Encoding method, TEXT string +024 "M" (8 characters): +025 "F" (examples: "MFM ", "RL27") +026 "M" 027-02B >0 14. Reserved: +02C-03B >0 A-20 Software Design Notes Data Structures Surface analysis parameters (based on media characteristics): ------------------------------------------------------------- 15. Number of reads per read type: +03C LSB byte +03D MSB byte 16. Allowable soft errors as percent of total +03E LSB byte reads per read type: +03F MSB byte 17. Allowable soft errors as percent of total +040 LSB byte reads per data pattern: +041 MSB byte 18. Allowable soft errors as percent of total +042 LSB byte reads: +043 MSB byte 19. Effective surface analysis margining combinations. Each two byte set of flags specifies a test read combination (if no bits are set then no read is performed). LSB byte: -------- bit: 7654 3210 19a. Bit 0: Nominal read xxxx xxxN 19b. Bit 1: Offset forward 1 xxxx xxNx 19c. Bit 2: Offset forward 2 xxxx xNxx 19d. Bit 3: Offset reverse 1 xxxx Nxxx 19e. Bit 4: Offset reverse 2 xxxN xxxx 19f. Bit 5: Strobe early 1 xxNx xxxx 19g. Bit 6: Strobe early 2 xNxx xxxx 19h. Bit 7: Strobe late 1 Nxxx xxxx MSB byte: --------- bit: 7654 3210 19i. Bit 0: Strobe late 2 xxxx xxxN 19j. Bit 1-7: Reserved NNNN NNNx 19k. Combination #0 .........................+044 LSB byte +045 LSB byte 19l. Combination #1 .........................+046 LSB byte +047 LSB byte 19m. Combination #2 .........................+048 LSB byte +049 LSB byte 19n. Combination #3 .........................+04A LSB byte +04B LSB byte 19o. Combination #4 .........................+04C LSB byte +04D LSB byte 19p. Combination #5 .........................+04E LSB byte +04F LSB byte 19q. Combination #6 .........................+050 LSB byte +051 LSB byte 19r. Combination #7 .........................+052 LSB byte +053 LSB byte A-21 Data Structures Software Design Notes 20. Worst case patterns for surface analysis: 20a. Pattern #0 .............................+054 LSB byte +055 MSB byte 20b. Pattern #1 .............................+056 LSB byte +057 MSB byte 20c. Pattern #2 .............................+058 LSB byte +059 MSB byte 20d. Pattern #3 .............................+05A LSB byte +05B MSB byte 20e. Pattern #4 .............................+05C LSB byte +05D MSB byte 20f. Pattern #5 .............................+05E LSB byte +05F MSB byte 20g. Pattern #6 .............................+060 LSB byte +061 MSB byte 20h. Pattern #7 .............................+062 LSB byte +063 MSB byte 21. Reserved: +064-3FF >0 FMT block #1-8: ("MAP" area, lists all media defects) ------------------------------------------------------ offset value -------------- 22. Total number of defects in the map: +400 LSB byte +401 MSB byte 23. Drive serial number (12 character text +402 "X" string): +403 "X" : +40D "X" 24. Original date of formatting: +40E "M" (8 char. text string; format= "MmDdYyyy") +40F "m" +410 "D" +411 "d" +412 "Y" +413 "y" +414 "y" +415 "y" 25. Latest date of formatting: +416 "M" (8 char. text string; format= "MmDdYyyy") +417 "m" +418 "D" +419 "d" +41A "Y" +41B "y" +41C "y" +41D "y" A-22 Software Design Notes Data Structures 26. Reserved: +41E-41F >0 27. Defect entries, 16 bytes each, in ascending order: +420-end (ascending order of cylinder/head/byte_ from_index) Up to 511 entries are accomodated. Each entry contains the following: 27a. Defect head address (1 byte number) entry +00 byte 27b. Defect cylinder address (3 byte entry +01 MDL byte number) entry +02 MDH byte entry +03 MDB byte 27c. Defect head address (1 byte number) entry +03 byte 27d. Defect displacement from index entry +04 LSB byte (number of bytes): entry +05 MDL byte entry +06 MDH byte entry +07 MSB byte 27e. Defect length (number of bits; entry +08 MSB byte >FF = 255 bits or longer) 27f. Reserved: entry +09-0F >0 A-23 Data Structures Software Design Notes A.3 MICRO-LOAD PARTITION FORMAT SPECIFICATION FOR THE EXPLORER II PROCESSOR A.3.1 Introduction. A.3.1.1 Scope. This specification defines the format for microcode files and partitions for the Explorer II and other processors which use the TI Lisp Microprocessor (tm). (Lisp Microprocessor is a trademark of Texas Instruments Incorporated.) This is the source document for information necessary to produce system utilities such as assemblers, MCR file-to-partition functions, and ahy ROM or processor down-loading programs. This standardized format is to be used since ROM resident system booting operations can not be changed, and it is expensive to support variations on utilities (assembler, spyport, mcr-loader, etc.). NOTE The maximum length of a microcode partition is limited to one megabyte due to limitations on memory space available during booting. This format for microcode partitions is slightly different than that of the Explorer I processor. This is due to differences in the processor architecture and in order to improve the robustness of booting for newer products. The term microload is used to indicate the microcode object file or the microcode disk partition format. A.3.1.2 Reference Documents. The following documents provide reference materiel necessary to understand the implications and applications of the information presented in this document. 1. NuBus System Architecture Specification 2536702-0001 2. Explorer II Processor Specification 2540834-0001 A-24 Software Design Notes Data Structures 3. Explorer Lisp Microprocessor Specification A.3.2 Overview. A microcode partition contains a number of types of data required to initialize the Explorer Lisp Microprocessor class of processors. The first section of the partition contains a Processor ID value (unique per processor type, and matches the Processor Type Value in the target processor's Configuration ROM), the assembly version number, a partition length, and checksum values. Additional sections contain a variety of information to initialize various memories and registers in the Lisp Microprocessor such as the local I/O address space on the processor board and virtual memory. ROM and spyport loaders use the microcode partition sections to perform specific Lisp Microprocessor, board, and system memory initializations. The following sections may be contained within the microload partition: Microcode Partition Header (required) Microcode Instruction Memory (required) Dispatch Memory (optional) M & A Memories (optional) Tag Memory (optional) Main Memory (optional) Input/Output Space memory (optional) Input/Output Space Initialization (optional) Auxiliary Data (optional) Entry Data (required) A microcode partition is formed of contiguous sections with no top level or embedded pointers to the individual section. Each section is processed in order. Optional sections may be repeated any number of times within a given microload and are located anywhere between the header and entry data sections. Since multiple sections of any given type may coexist in same the microload, data of later processed sections may overwrite any previously processed section. The processing of the microload will continue sequentially until the Entry Data section is read. A-25 Data Structures Software Design Notes The following diagram delineates sections within a microcode partition. Note that this example does not demonstrate that most section types can appear more that once or in any order within the microload. The ROM and spyport loaders are responsible for processing sections sequentially and to insure that the resultant data resides in the appropriate memories. The assembler is responsible for producing a file of the format described by this specification. All values in the format are stored in pure Little Endian form (i.e. ordered from least significant to most significant). A-26 Software Design Notes Data Structures start of partition +-------------------------------+ | Microcode Partition Header | | Section ID = #x0 | | processor ID | | version number | | active length | | checksum | +-------------------------------+ | Microcode Instruction Memory | | section ID = #x1 | | WCS Address | | number of I-Mem words | | instructions... | ====> Writable Control Store +-------------------------------+ | Dispatch Memory | | section ID = #x2 | | dispatch address | | number of D-Mem words | | dispatch values... | ====> Dispatch Memory +-------------------------------+ | A & M Memories | | section ID = #x3 | | A&M address | | number of A-Mem words | | values... | ====> A & M Memory +-------------------------------+ | Tag Memory | | section ID = #x4 | | tag class | | number of T-Mem classes | | tag values... | ====> Tag classifier Memory +-------------------------------+ | IO Space Initialization | | section ID = #x5 | | destination IO address | | number of words to write | | initial data value | ==(adjusted)=> IO space | insert memory offset option | | data increment | | address increment | +-------------------------------+ | IO Space Data | | section ID = #x6 | | destination IO address | | number of words | | address increment | | data values... | ==== IO space memory +-------------------------------+ | Main Memory | | section ID = #x7 | | destination virtual address | A-27 Data Structures Software Design Notes | number of VM words | | data | ====> Main memory +-------------------------------+ | Auxilliary Data | | section ID = #xA | | sub ID | | number of words | | values... | ====> Processor specific use +-------------------------------+ | Entry Data | | section ID = #x0E0F | | micro PC | ====> Lisp Microprocessor | | micro PC | MCR | ====> Lisp Microprocessor | | MCR +-------------------------------+ A.3.3 Detail Section Definitions. The following paragraphs describe the format and uses of each section of the microcode partition. This section is intended to be required for all Explorer Lisp Microprocessor class processors. A.3.3.1 Microload Header Section. The Header section is used identify the microload as a microcode partition or object file. Information such as the target processor-OD, microcode assembly version number, and active length are all stored here. A checksum is provided to verify the data integrity of a microcode partition at boot time. The microload Header section must appear as the first section in the Partition. Only one microload Header section is allowed in any given microload. A Header section contains the following fields: byte value offset function or format description --------------------------------------------------------------- #x0 Section ID #x0 Identifies the Header section. #x4 Processor ID 32 bit Bits <15:00> contain value #x8 Version number 32 bit Microcode assy. version no. #xC Active Word Length 32 bit Total length of active data in 32 bit words (a value of -1 indicates that the checksum is not supported) A-28 Software Design Notes Data Structures #x10 Checksum 32 bit Checksum of all active data (Zero if not supported) The Processor ID is used to verify that a given microload is targeted for the booting processor. The Processor ID is a 16 bit value and resides in bits <15:00>. The Processor ID must exactly match the Processor Type field in the target processor's Configuration ROM. The Version number is a binary value equal to the current microload assembly version. This is determined by the assembler from the last assembly for a given control file. This count begins with 1. The Active Word Length specifies how many words (in 32 bit values) beyond the Checksum are to be processed for the load-time Checksum calculation (initial value = 0, add each word, ignoring overflow). The match must be exact. Note that data stored in the partition beyond the end of the Active Word Length is not processed or validated by ROM boot mechanisms and must not cause the total length of the microcode partition to exceed one megabyte. An active length of -1 indicates that the checksum calculation is disabled. In this case, a value of 0 is provided for the Checksum. A.3.3.2 Instruction Memory Section. The Instruction Memory section contains the microcode words to be stored in Writable Control Store [WCS]. Each 64 bit Instruction Memory [I-mem] word is stored in two consecutive 32 bit words in the partition, and four consecutive 16 bit words in the MCR file (least significant bits first). The WCS Address specifies the I- Mem destination address into which the first microcode word is written. Successive I-Mem instructions are written into ascending addresses until Number of Words has been transferred. Parity for each I-Mem word is generated by the assembler and is not checked during loading. One or more instruction memory sections must exist within a microload. However, only the last section of this type before the Entry Data section shall be loaded by the ROM load mechanism. A Microcode section contains the following fields: A-29 Data Structures Software Design Notes byte value offset function or format description --------------------------------------------------------------- #x0 Section ID #x1 Identifies the microcode section #x4 WCS Address 32 bit Starting microcode address #x8 Number of Words 32 bit Total number of 64-bit microcode words #xC+8N LSB of instruction 32 bit Bits <31:00> of an instruction #x10+8N MSB of instruction 32 bit Bits <63:32> of an instruction (N ranges 0 to Number of Words) A.3.3.3 Dispatch Section. The Dispatch section contains data for the dispatch instructions to be stored in the internal Lisp Microprocessor Dispatch RAM. Each 18 bit dispatch word is stored in a 32 bit word in the partition. The Dispatch Address specifies the D-Mem destination address into which the first dispatch word is written. Successive D-Mem words are written into ascending addresses until Number of Words have been transferred. The upper bits of each 32-bit word in the partition, bits <31:18>, are ignored during the booting. Zero or more Dispatch memory sections may be present in any given microload. Later sections may overwrite earlier sections. Dispatch memory sections must appear before the Entry Data section and after the Microload header. A Dispatch section contains the following fields: A-30 Software Design Notes Data Structures byte value offset function or format description --------------------------------------------------------- #x0 Section ID #x2 Identifies a Dispatch section #x4 Dispatch Address 32 bit Initial dispatch address #x8 Number of Words 32 bit Number of dispatch words #xC+4N Dispatch value 32 bit Bits <17:00> are dispatch value (N ranges 0 to Number of Words) A.3.3.4 A&M Memory Section. The A&M Memory section contains the initial A&M Memory values to be stored in the internal Lisp Microprocessor A&M Memory RAM. The A&M Memory Address specifies the address for first A&M Memory word. Successive A&M Memory words are written into ascending addresses until Number of Words has been transferred. Data values with addresses 0 to #x3F are also written into M-Memory. Data values above #x3F are written into A-Memory only. Zero or more A&M Memory sections may be present in any given microload. Later sections may overwrite earlier sections. A&M memory sections must appear before the Entry Data section and after the Microload header. An A&M memory section contains the following fields: byte value offset function or format desciption ------------------------------------------------------------- #x0 Section ID #x3 Identifies a A&M Memory section #x4 A&M Memory Address 32 bit Starting A&M Memory address #x8 Number of Words 32 bit Number of A&M Memory values #xC+4N A&M Memory value 32 bit Initial A&M Memory value (N ranges 0 to Number of Words) A-31 Data Structures Software Design Notes NOTE On the Explorer II processor, the highest 8 A-Memory locations (#x3F8 through #x3FF) are reserved for passing system boot information to the downloaded code and are therefore not loaded from the A&M Memory section even if the A&M memory section contains values for these locations. Likewise, because their use is required during booting, locations 0-3 are alsu not actually initialized from the MCR. Location 0's initial value is indeterminate. A.3.3.5 Tag Classifier Section. The Tag Classifier section contains the Tag Classifier data values that are stored in the Lisp Microprocessor's internal Tag Classifier RAM. Each Tag Class specifies 64 bits of data (2-bits for each of 32 data types) to be stored in the Tag Classifier RAM. Tag Class data is divided into four quarters, each of which occupies the most significant 16-bits (<31:16>) of four consecutive 32 bit words in a Tag Classifier section. The Tag Class Address specifies the Tag Classifier memory destination address for first Tag Class. Successive Tag Classes are then written into memory until Number of Classes have been written. Zero or more Tag Classifier Memory sections may be present in any given microload. Later sections may overwrite earlier sections. Tag Classifier memory sections must appear before the Entry Data section and after the Microload header. A Tag Classifier memory section contains the following fields: byte value offset function or format description ------------------------------------------------------------------ #x0 Section ID #x4 Identifies a Tag Classifier Memory section #x4 Tag Class 32 bit Starting Tag Class #x8 Number of Classes 32 bit Number of Tag Classes #x0C+10N Tag Classifier Value 32 bit Quarter-0 T-mem<15:00> #x10+10N Tag Classifier Value 32 bit Quarter-1 T-Mem<31:16> #x14+10N Tag Classifier Value 32 bit Quarter-2 T-Mem<47:32> #x18+10N Tag Classifier Value 32 bit Quarter-3 T-Mem<63:48> (N ranges 0 to Number of Classes) (Qn = Tag Class Quad) A-32 Software Design Notes Data Structures A.3.3.6 I/O Space Initialization Section. The I/O Space Initialization section contains parameters to specify patterns that are to be written into the local address (I/O) space. If bit <31> of the Insert Memory Offset word is set (=1) then at boot time the Initial Data value is adjusted by an LDB of the NuBus address of the current system memory into the Initial Data value. Bits <09:00> of the Insert Memory Offset word are used to generate the rotation length and count for the LDB. This feature, in conjunction with the Data and Address Increment values, supports initialization of the Virtual Memory Maps by the ROM mechanisms. The (potentially adjusted) data value is written into the Starting Address. After each write the data value is adjusted by adding the Data Increment value to allow initializations with values that include zero or mroe incrementing fields. Also, the destination address is adjusted after each write by adding the Address Increment value. This is necessary due to the manner in which most of the arrays on processor boards are addressed in IO space. Writing and adjusting of data and addresses continues until Number of Words have been written. Zero or more I/O Space Initialization sections may be present in any given microload. Later sections may overwrite earlier sections. I/O Space Initialization sections must appear before the Entry Data section and after the Microload header. An I/O Space Initialization section contains the following fields: A-33 Data Structures Software Design Notes byte value offset function or format description ------------------------------------------------------------ #x0 Section ID #x5 Identifies an I/O Space Initialization section #x4 Starting Address 32 bit I/O Space destination address #x8 Number of words 32 bit Number of 32-bit words to write #xC Initial Data 32 bit Initial data value for writes #x10 Insert Memory Offset 32 bit Bit <31> : 1= enable insertion Bit <09:05> : rotation length Bit <04:00> : rotation count #x14 Data Increment 32 bit Add to data value after each write #x18 Address Increment 32 bit Add to address value after each write A.3.3.7 I/O Space Data Section. The I/O Space Data section contains data that are used to load the various memories in I/O space. This can be used to initialize the Transport RAM and other IO space features. The Starting Address is an absolute Lisp Microprocessor IO space address. Data Values are copied from the section into IO space. After each write, the destination address is adjusted by adding the Address Increment value. This is necessary due to the manner in which most of the arrays on processor boards are addressed in IO space. Writing and adjusting of addresses continues until Number of Words have been written. Zero or more I/O Space Data sections may be present in any given microload. Later sections may overwrite earlier sections. I/O Space Data sections must appear before the Entry Data section and after the Microload header. An I/O Space Data section contains the following fields: A-34 Software Design Notes Data Structures byte value offset function or format description -------------------------------------------------------------- #x0 Section ID #x6 Identifies an I/O Space Data section #x4 Starting Address 32 bit Destination I/O address #x8 Number of words 32 bit Number of 32 bit words to write #xC Address Increment 32 bit Add to destination address value after each write #x10+4N Data Value 32 bit Data values to be written (N ranges 0 to Number of Words) A.3.3.8 Main Memory Section. The Main memory section contains data values to be stored in this processor's main memory. The Source Data Values are stored as 32-bit values. The Destination Address is adjusted from a virtual (word) to a physical (byte) value and then added to the NuBus address of the system memory determined by the booting mechanism (the System Test and Boot Master or utilities such as Spyport software which also load MCH's) to belong to this processor. Successive words of Source Data Values are transferred sequentially until Number of words have been written. Zero or more Main Memory sections may be present in any given microload. Later sections may overwrite earlier sections. Main Memory sections must appear before the Entry Data section and after the Microload header. A Main Memory section contains the following fields: A-35 Data Structures Software Design Notes byte value offset function or format description ------------------------------------------------------------- #x0 Section ID #x7 Identifies a Main Memory section #x4 Destination Address 32 bit Virtual (word) address #x8 Number of 32-bit words 32 bit Number of words to write #xC+4N Data Value 32 bit Data (N ranges 0 to Number of Words) A.3.3.9 Auxiliary Data Section. The Auxiliary Data section contains processor specific data. The use of this data will be defined by individual processor boot mechanism and system specifications. The Sub ID code allows a processor to have more than one type of Auxiliary section. The section contains Number of Words of Data Values whose format and use are processor dependent. The Explorer II processor supports a Required Floating Point Processor Auxiliary Data section (sub-id type = 1). If this section is present in a partition, then the first data word of this section must exactly match the type floating point option present. Floating point option boards identify themselves via a three bit field in the Explorer II External Control Register. The Required Floating Point Processor Auxiliary Data section must be used to prevent microcode which requires a specific floating point option board from being loaded, only to crash when a different option board (or more likely none at all) is present. Additional Auxiliary Data values beyond the first word are ignored, as are Auxiliary Data sections of other sub-id types. They may therefore transport various types of data specific to a MCR partition (such as crash table or build information) bit not needed during booting. Zero or more Auxiliary Data sections may be present in any given microload. Auxiliary Data sections must appear before the Entry Data section and after the Microload header. An Auxiliary Data section contains the following fields: A-36 Software Design Notes Data Structures byte value offset function or format description ------------------------------------------------------------------ #x0 Section ID #xA Identifies a Auxiliary Data section #x4 Sub ID 32 bit Differentiates sub sections (processor dependent) #x8 Number of words 32 bit Number of 32 bit values in remainder of section #xC+4N Data Values 32 bit Data values (N ranges 0 to Number of Words) A.3.3.10 Entry Data Section. The Entry Data section serves as a marker to indicate the end of the microload. It contains the processor's initial Micro PC and initial Machine Control Register values. Note that both these values are required, as they shall be set as the starting state of the Lisp Microprocessor as the last act of the booting mechanisms. Exactly one Entry Data section must be present in a partition and it must appear after all other sections which require loading at boot time. Additional sections may be present following the Entry Data section to carry auxiliary information about each particular microload. The Entry Data section contains the following fields: byte value offset function or format description -------------------------------------------------------------- #x0 Section ID #xEOF Identifies the Entry Data section #x4 Micro PC 32 bit Initial Micro Program Counter #x8 MCR 32 bit Initial Machine Control Register value A-37